1. Field of the Invention
The invention relates to a semiconductor integrated circuit made up by integrating a plurality of N channel MOSFETs with a plurality of P channel MOSFETs, and more particularly, to a semiconductor integrated circuit comprising the plurality of the respective channel MOSFETs, each incorporating at least a MOSFET having a different threshold voltage, and also to a testing method thereof.
2. Description of the Related Art
Portable information equipment, typically such as PHS (personal handy-phone system) and PDA (portable data assistant), have recently come into widespread use. A semiconductor integrated circuit (referred to hereinafter as IC) is in use as one of the components of the portable information equipment. There has been a strong demand that the IC can achieve reduction in power consumption without degrading its performance in respect of processing speed.
An IC using the CMOS technology is known for its lower consumption of power in comparison with an IC using the bipolar technology or the EDMOS technology.
However, even with the IC using the CMOS technology, the magnitude of power consumption thereof has come to pose a problem as a result of shift of operation frequencies of ICs to higher frequencies taking place lately.
The power consumption P of a CMOS logic gate circuit in the IC using the CMOS technology is generally approximated by the following expression:
Pxe2x88x9dKxc2x7Cxc2x7Vdd2xc2x7f+I leakxc2x7Vddxe2x80x83xe2x80x83(1)
where K=switching probability,
C=output load capacity of the CMOS logic gate circuit, Vdd=power source voltage,
f=operation frequency, and
I leak=subthreshold leak current.
The subthreshold leak current will be further described hereinafter. A symbol xe2x80x9cxc2x7xe2x80x9d in expression (1) denotes multiplication, and the same applies to other expressions referred to later.
When the IC is in an operating mode (for example, when the CMOS logic gate circuit is in an operating state upon supply of a clock signal of a given frequency thereto), a first term of the expression (1) becomes dominant, and power consumption thereof will be proportional to the square of the power source voltage Vdd. On the other hand, when the IC is in a standby mode (when the operation of the CMOS logic gate circuit is in a suspended state upon supply of a clock signal thereto being inhibited), a second term of the expression (1) becomes dominant since the operation frequency turns to zero. As is evident from the expression (1), by lowering the power source voltage Vdd, the power consumption, particularly when the IC is in an operating mode, can be significantly reduced. Accordingly, there has been an increasing demand for ICs used in portable information equipment that can be operated at lower power source voltages.
As described in the foregoing, the power consumption of the IC can be reduced by lowering the power source voltage Vdd. However, the power source voltage Vdd at a reduced level results in an increase of gate propagation delay time tpd of the CMOS logic gate circuit making up the IC. The gate propagation delay time tpd of the CMOS logic gate circuits is generally approximated by the following expression:
tpd=Cxc2x7Vdd/(Vddxe2x88x92Vt)xcex1xe2x80x83xe2x80x83(2)
where C=output load capacity of the CMOS logic gate circuit,
Vdd=power source voltage,
Vt=threshold voltage of switching MOSFETs, and
xcex1=factor determined, depending on the generation of a device 1xe2x89xa6xcex1xe2x89xa62.
As is evident from the expression (2), the power source voltage Vdd at a reduced level results in a gradual increase of the gate propagation delay time tpd. It is further shown that if the power source voltage Vdd is lowered close to the threshold voltage Vt of a MOSFET, a denominator on the right side of the expression (2) becomes small in value, resulting in a significant increase in the gate propagation delay time tpd. It follows therefore that the threshold voltage Vt of the MOSFET needs to be lowered according as the power source voltage Vdd is lowered in order that the power source voltage Vdd is lowered without causing an increase in the gate propagation delay time tpd.
Meanwhile, as indicated by the second term of the expression (1), the power consumption (referred to hereinafter as standby power consumption) of the CMOS logic gate circuits when the IC is in a standby mode is substantially determined by leak current Ileak. (referred to generally as subthreshold leak current) occurring when a voltage between the gate and the source of the MOSFET is at 0V. The subthreshold leak current Ileak is generally approximated by the following expression:
Ileakxe2x88x9de x p{xe2x88x92Vt (S/In 10)}xe2x80x83xe2x80x83(3)
where Vt=the threshold voltage of a MOSFET, and
S=subthreshold factor, one of numerical values indicating the characteristics of a MOSFET, and more specifically, a numerical value indicating the currentxe2x80x94voltage characteristic in a region where a voltage between the gate and the source of the MOSFET is not higher than the threshold voltage Vt. With MOSFETs of the submicron order, the numerical value is generally on the order of 80 to 90 mV/decade.
As is evident from the expression (3), it is shown that if the threshold voltage Vt is set at low levels, the subthreshold leak current Ileak will increase exponentially. For example, if the threshold voltage of a MOSFET making up an IC comprising a CMOS logic gate circuit is lowered by 0.3V, this will result in an increase of the subthreshold leak current Ileak occurring when the IC is in a standby mode by three or four orders of magnitude.
As described in the foregoing, there is a trade-off relationship between the subthreshold leak current Ileak when the threshold voltage Vt is changed and the gate propagation delay time tpd. With ICs comprising a CMOS logic gate circuit, the threshold voltage Vt is generally set such that the gate propagation delay time tpd as required can be achieved while meeting the standby power consumption as allowed in product specification and so forth. It has become extremely difficult, however, to reconcile the subthreshold leak current Ileak which is satisfactory with the gate propagation delay time tpd which is also satisfactory in the face of the recent demand for lowering the power source voltage Vdd.
In connection with the CMOS technology, there has been disclosed in the following literature a technology whereby the standby power consumption can be reduced without sacrificing operation speed characteristic (for example, the gate propagation delay time tpd); the title of the literature: xe2x80x9c1-V Power Supply Highxe2x80x94Speed Digital Circuit Technology with Multithreshold xe2x80x94Voltage CMOSxe2x80x9d.IEEE Journal of Solid-State Circuits 30[8], pp. 847-854, 1995.
The technology disclosed in the literature described above is called a Multixe2x80x94Threshold Voltage CMOS (referred to hereinafter as MT CMOS) technology. The MT CMOS technology disclosed in the literature described above will be briefly described hereinafter.
In an IC using the MT CMOS technology, a power source voltage is supplied to the logic gate circuit thereof via a pseudo power source voltage line on the high potential side and a pseudo power source voltage line on the low potential side.
The logic gate circuit comprises P channel MOSFETs and N channel MOS FETs, both having low threshold voltages. A power source voltage on the high potential side is supplied to the pseudo power source voltage line on the high potential side via a switch made up of a P channel MOSFET having a threshold voltage higher than that of the P channel MOSFETs making up the logic gate circuit. A power source voltage on the low potential side is supplied to the pseudo power source voltage line on the low potential side via a switch made up of a N channel MOSFET having a threshold voltage higher than that of the N channel MOSFETs making up the logic gate circuit.
When the N channel MOSFETs making up the IC and the switch made up of the N channel MOSFET are looked at as four-terminal devices, each having terminals such as the drain, source, gate, and substrate, the power source voltage on the low potential side is supplied to the substrate terminal of the respective N channel MOSFETs via a P well layer or a P type semiconductor substrate (if a P type semiconductor substrate is in use).
Also, when the P channel MOSFETs making up the IC and the switch made up of the P channel MOSFET are looked at as four-terminal devices, each having terminals such as the drain, source, gate, and substrate, the power source voltage on the high potential side is supplied to the substrate terminal of the respective P channel MOSFETs via a N well layer or a N type semiconductor substrate (if a N type semiconductor substrate is in use).
When the IC using the MT CMOS technology, having the configuration described above, is in an operating mode, the N channel MOSFET and the P channel MOSFET serving as switches are turned to a conducting state. Accordingly, the pseudo power source voltage line on the high potential side will be at a potential substantially equivalent to the power source voltage on the high potential side due to the power source voltage on the high potential side supplied via the P channel MOSFET acting as a switch. Similarly, the pseudo power source voltage line on the low potential side will be at a potential substantially equivalent to the power source voltage on the low potential side due to the power source voltage on the low potential side supplied via the N channel MOSFET acting as a switch. Thus, the logic gate circuit is supplied with the power source voltage on the high potential side and the power source voltage on the low potential side, respectively, enabling logic operation as desired to be performed.
Since the threshold voltage of the N channel MOSFETs and the P channel MOSFETs, making up the logic gate circuit, are set at low levels, operation can be performed at a low power source voltage Vdd without causing an increase in the gate propagation delay time tpd in contrast to a case where the N channel MOSFETs and the P channel MOSFETs, having high threshold voltages, are used. That is, with this type of IC, power consumption when the IC is in an operating mode can be reduced while maintaining speed performance equivalent to that for a case where the N channel MOSFETs and the P channel MOSFETs, having high threshold voltages, are used in the logic gate circuit.
With the IC in a standby mode, the N channel MOSFET and the P channel MOSFET serving as switches are turned to a nonconducting state. Accordingly, magnitude of the subthreshold leak current Ileak flowing from the power source voltage on the high potential side to the power source voltage on the low potential side will be determined depending on the subthreshold current characteristic of the N channel MOSFET and the P channel MOSFET, making up the switches described above, in a nonconducting state. As described in the foregoing, since the threshold voltage of the N channel MOSFET and that of the P channel MOSFET, respectively, making up the switches, are set at high levels, the subthreshold leak current Ileak can be made small in value. That is, although the logic gate circuit is made up of MOSFETs having low threshold voltages, the subthreshold leak current Ileak can be made equivalent in value to that for a case where the logic gate circuit is made up of MOSFETs having high threshold voltages.
As described hereinbefore, with the IC using the MT CMOS technology, it will be possible to reduce power consumption in an operating mode by lowering the power source voltage Vdd, to maintain delay performance without increasing the gate propagation delay time tpd of the logic gate circuit, and to reduce the standby power consumption due to the effect of the subthreshold leak current when in an standby mode.
The IC using the MT CMOS technology has excellent characteristics as described above, but is faced with a problem of concern at the time of testing. That is, an IDDQ test which has recently been brought into use for testing products on a mass production basis prior to shipment in order to improve a failure detection ratio of large scale logic ICs, in particular, is not applicable thereto.
The IDDQ test takes advantage of the characteristics of a logic gate circuit, made up of MOSFETs having high threshold voltages, whereby in the case of conforming products, a power source current IDD (current flowing from the power source voltage on the high potential side to the power source voltage on the low potential side) is only a leak current of very small magnitude (for example, in the range of several nA to several tens xcexcA for the whole IC), determined by the subthreshold leak current of the respective MOSFETs when the MOSFETs, making up the logic gate circuit, are not in a state of switching operation.
More specifically, in several patterns of stable conditions wherein the output voltage of respective logic gate circuits within the IC is set at a high level or a low level, a current value of the power source current IDD is measured. In case of a measured current value of the power source current IDD being sufficiently greater than a preestimated current value of the leak current, it can be determined that something abnormal (shorts between connections, breaks in connections, and so forth) has occurred inside the IC. That is, by measuring the power source current IDD when the IC is in a standby mode, any physical defect inside the IC can be detected.
In a common 0.25 xcexcm class IC using the CMOS technology, with 100,000 gates integrated therein, the power source current IDD, dependent on the subthreshold leak current, is on the order of 100 nA to 10 xcexcA when the threshold voltage value of the N channel MOSFETs and the P channel MOSFETs are set at 0.5V and xe2x88x920.5V, respectively. Meanwhile, in case of abnormality inside the IC, for example, a short between connections, a short current value will increase by orders of magnitude to as much as 100 xcexcA to 10 mA. As the short current will be superimposed on the power source current IDD, measurement of a current value of the power source current IDD enables detection on whether or not abnormality has occurred inside the IC to be made with ease.
In detection of failure inside the IC, the IDDQ test has a high failure detection ratio in comparison with the conventional logical function test whereby logical output values of the IC against input in the logical test pattern series are checked against estimated logical values, or the conventional function test, making it possible to shorten a test period, and to reduce testing costs. Taking into account a considerable increase in the integration scale of the logical gate circuit, in particular, resulting from miniaturization of the IC production process, the merit of using the IDDQ test is considered tremendous.
Now, the reason why the IDDQ test described in the foregoing can not be applied to the IC using the MT CMOS technology is described hereinafter.
When the IC is in an operating mode, the power source voltage on the high potential side and the power source voltage on the low potential side are supplied to the pseudo power source voltage line on the high potential side and the pseudo power source voltage line on the low potential side, respectively, by turning the P channel MOSFET and the N channel MOSFET, acting as the switches, into a conducting state. Consequently, the logic gate circuits inside the IC will be in a state enabling logic operation, and an output voltage of the respective logic gate circuits can be set at a high voltage level or a low voltage level. However, since the logic gate circuits of the IC using the MT CMOS technology are made up of MOSFETs having a low threshold voltage, the subthreshold leak current of the respective MOSFETs will become large in value. This causes the power source current IDD for the whole IC to become fairly large even when the IC is not in a state of executing logical operation.
For example, in a common 0.25 xcexcm class IC using the CMOS technology, with 100,000 gates integrated therein, the power source current IDD, dependent on the subthreshold leak current, is on the order of 100 xcexcA to 10 mA when the threshold voltage value of the N channel MOSFETs and the P channel MOSFETs are set at 0.2V and xe2x88x920.2V, respectively. Accordingly, even if there should occur failure to a part of the logic gate circuit such as a short between connections, and a resultant short leak current is on the order of 100 xcexcA to 10 mA, superimposed on the power source current IDD, such a short leak current will be hidden in the power source current IDD, dependent on the subthreshold leak current. As a result, it becomes extremely difficult or impossible to detect failure by measuring the power source current IDD.
Further, when the IC is in a standby mode, the P channel MOSFET and the N channel MOSFET, acting as the switches, are turned into a nonconducting state. Consequently, since neither the power source voltage on the high potential side nor the power source voltage on the low potential side is supplied to the logic gate circuits inside the IC, it is impossible to detect failure, if any, occurring to the logic gate circuits on the basis of the power source current IDD.
As described hereinbefore, with the IC using the MT CMOS technology, the power source current IDD, based on the subthreshold leak current, becomes larger, when in an operating mode, in comparison with that for a IC having logic gate circuits made up of MOSFETs having common high threshold voltages, making it difficult or impossible to detect failure occurring to the logic gate circuits. While in a standby mode, any failure occurring to the logic gate circuits can not be detected on the basis of the power source current IDD.
Thus the IDDQ test can not be applied to the IC using the MT CMOS technology, in particular, to ICs having highly integrated logic gate circuits. This will result in deterioration in a failure detection ratio at pre-delivery tests for products manufactured on a mass production basis, or there will arise needs for additional massive function tests to improve a failure detection ratio, causing an increase in testing time and testing costs.
It is an object of the invention to provide a semiconductor integrated circuit capable of improving a failure detection ratio to overcome problems described in the foregoing.
It is another object of the invention to provide a semiconductor integrated circuit capable of achieving the object described above while inhibiting an increase in the chip size of the semiconductor integrated circuit.
It is still another object of the invention to provide a method of testing a semiconductor integrated circuit, enabling a failure detection ratio to be improved without causing an increase in testing time and testing costs.
To this end, the invention provides a semiconductor integrated circuit made up by integrating a plurality of first conduction type MOS transistors with a plurality of second conduction type MOS transistors, comprising:
a first power supply line for supplying a first power source voltage;
a first MOS transistor of the plurality of the first conduction type MOS transistors, having a first threshold voltage, and provided with a gate electrode, a first electrode, and a second electrode, the first electrode being connected to the first power supply line;
a first pseudo power supply line connected to the second electrode of the first MOS transistor;
an internal logic circuit comprising at least a second MOS transistor of the plurality of the first conduction type MOS transistors, having a second threshold voltage lower than the first threshold voltage, and supplied with the first power source voltage via the first pseudo power supply line; and
a first terminal for supplying a suitable voltage to a substrate terminal of the second MOS transistor.
Also, the semiconductor integrated circuit according to the invention may also comprise:
a second power supply line for supplying a second power source voltage, different from the first power source voltage;
a third MOS transistor of the plurality of the second conduction type MOS transistors, having a third threshold voltage, and provided with a gate electrode, a first electrode, and a second electrode, the first electrode being connected to the second power supply line; and
a second pseudo power supply line connected to the second electrode of the third MOS transistor, for supplying the second power source voltage to the internal logic circuit, said internal logic circuit comprising at least a fourth MOS transistor of the plurality of the second conduction type MOS transistors, having a fourth threshold voltage lower than the third threshold voltage.
The semiconductor integrated circuit may further comprise a second terminal for supplying a suitable voltage to a substrate terminal of the fourth MOS transistor.
With the semiconductor integrated circuit according to the invention, the first power source voltage and the second power source voltage may be applied to a substrate terminal of the first MOS transistor and the third power source voltage, respectively, or the first power supply line and the second power supply line may be connected to the substrate terminal of the first MOS transistor and the third power source voltage, respectively.
The semiconductor integrated circuit according to the invention may further comprise a third terminal and a fourth terminal connected to the first power supply line and the second power supply line, respectively, the third terminal and the fourth terminal being connected to the first terminal and the second terminal, respectively, by means of wire bonding.
Further, the semiconductor integrated circuit according to the invention may further comprise a voltage generation circuit for supplying the substrate terminal of the first and the third MOS transistors with a predetermined voltage according to a test signal inputted via the first terminal and the second terminal, respectively.
Still further, with the semiconductor integrated circuit according to the invention, the first and second MOS transistors may be formed in a first well of the second conduction type, formed in a semiconductor substrate, and the first terminal may be connected to the first well, or the first MOS transistor may be formed in a first well of the second conduction type, formed in a second conduction type semiconductor substrate while the second MOS transistor is formed in a third well of the second conduction type, within a second well of the first conduction type, formed in the second conduction type semiconductor substrate, the first terminal being connected to the third well.
Now, with a method of testing a semiconductor integrated circuit, according to the invention, the first power source voltage is supplied to the first power supply line, the first MOS transistor is turned to a conducting state, and a voltage so as to increase a threshold voltage of the second MOS transistor is supplied to the substrate terminal of the second MOS transistor by use of the first terminal before measuring a value of current flowing through the internal logic circuit.
Further, with the method of testing a semiconductor integrated circuit, the first power source voltage may be supplied to the first power supply line, the second power source voltage may be supplied to the second power supply line, the first and third MOS transistors may be turned to a conducting state, a voltage so as to increase the threshold voltage of the second MOS transistor may be supplied to the substrate terminal of the second MOS transistor by use of the first terminal while a voltage so as to increase a threshold voltage of the fourth MOS transistor is supplied to the substrate terminal of the fourth MOS transistor by use of the second terminal before measuring a value of current flowing through the internal logic circuit.